module debounce(clk, in, out);
input clk;
input [12:0] in;
output [12:0] out;

reg [1:0] count;
reg [12:0] inbuf;
reg [12:0] out;

always @ (posedge clk)
begin
  if (in != inbuf)
  begin
    count<=0;
    inbuf<=in;
  end
  else
  begin
    if (count == 2'b10)
      out<=inbuf;
    if (count != 2'b11)
      count<=count+1;
  end
end


endmodule